As you already know, in our group here at Chalmers, we are primarily interested in studying the surface states in hybrid devices involving topological insulator(TI) nanowires and conventional superconductors. Although, in theory, TI should have an insulating bulk, this is not the case when it comes to experiments. In the case of the Bi2Se3 nanowire we use, there are Se vacancies that result in oxide formation and this, in turn, gives a doped bulk carrier which makes it challenging to study the surface transport. We have been trying to use different approaches for gating away the bulk contributions. Most of our approaches were not much successful due to various material and fabrication challenges and other requirements from the devices.
Recently we started considering exfoliated h-BN as potential gate dielectric material as the fabrication process after depositing the nanobelts will not involve temperatures over 150 degrees C (check image given above). In our initial tests, even though we could not get to the Dirac point in these Bi2Se3 nanobelts, we found that the h-BN is doing much better than other approaches we tried (see below). However, exfoliating h-BN and stamping them on pre-defined gate structures is a time-consuming process. This is where my remote secondment with Graphenea comes into the picture.
We fabricated two 20x20 mm chips with markers and local gate electrode arrays. This was then sent to Graphenea on 8th August. Due to personal reasons, I could not make a blog post about it till now. At Graphenea, they will deposit CVD grown all over the chip via wet transfer techniques. Also, as soon as they arrive back at Chalmers, we will deposit the nanowires on this chip to fabricate different kinds of devices and to check how effective gating CVD graphene is for our purposes.
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